The present invention relates to a semiconductor circuit having a current switch circuit and, more particularly, to a semiconductor circuit which includes a current switch circuit which imparts a latch function to an input buffer.
In the prior art, semiconductor devices frequently use current switch circuits for switching current paths in response to input signals. FIG. 1 shows the input buffer of a semiconductor memory device, which is frequently used in the prior art, and in which transistors Q1 and Q2, having their emitters commonly connected, form a current switch circuit. The levels of an input signal V.sub.IN1 and a reference voltage V.sub.BB usually have such a relationship as is shown in FIG. 2. The current of a current source I.sub.1 flows through the transistor Q1, when the input signal V.sub.IN1 is high, V.sub.IN1 (H), and through the transistor Q2 when the input signal V.sub.IN1 is low, V.sub.IN1 (L) Here, it is frequently necessary to give the input buffer such a latch function so as to receive an input signal only when a clock signal at a high or low voltage is fed from the system, as is disclosed in Japanese patent Laid-Open No. 58-222486, for example. FIG. 3 shows an example of the prior art, in which the input buffer serves as a latch. Here, the input signal is input to the position V.sub.IN1 whereas the clock signal is input to the position V.sub.IN2. In this example, the input signal V.sub.IN1 is introduced when the clock signal V.sub.IN2 is low. Next, the circuit operations of the prior art example shown in FIG. 3 will be briefly described. Now, if the clock signal V.sub.IN2 is low, the current of the current source I.sub.1 flows through a transistor Q3. At this time, the current of the current source I.sub.1 flows through the transistor Q1 or Q2, depending upon whether the input signal V.sub.IN1 is high or low, so that the output voltage V.sub.01 goes low or high. Next, if the clock signal V.sub.IN2 is high, the current of the current source I.sub.1 flows through a transistor Q4. The transistor, Q5 or Q6, that current flows through is determined by the base voltage of the respective transistors at the high voltage. A suitably level-shifted voltage is applied by a level shift circuit LS to the bases of the transistors Q5 and Q6 from the output signals V.sub.02 and V.sub.01. Therefore, if the output signal V.sub.01 is high when the voltage V.sub.02 is low, current flows through the transistor Q6, and the output signal is held as it was in the previous state. That is, the output of the buffer does not depend upon the input signal V.sub.IN1 when the clock signal V.sub.IN2 is high.
If the latching function is effected by a series gate, as shown in FIG. 3, high-amplitude signals cannot be processed because of the restrictions imposed by supply voltage and by transistor saturation. This problem will now be described in detail with specific values in circuits.
To speed up signal processing, it is frequently necessary to set the voltage amplitudes of the aforementioned output signals V.sub.01 and V.sub.02 at 2.6 V or higher, for example.
Let us assume that the voltage amplitudes of the output signals V.sub.01 and V.sub.02 must be no less than 2.6 V. If, at this time, the power supply V.sub.T1 is at 0 V, a node N1 or N2 is at -2.6 V. When the node N1 is at -2.6 V, the high voltage of the input signal V.sub.IN1 must be -2.6 V or lower so that the transistor Q1 will not reach saturation. This is because a transistor must have its collector voltage higher than its base voltage in normal use so that it may not reach saturation. If the voltage amplitude of the input signal V.sub.IN1 is at 0.4 V, its low voltage is -3.0 V so that the reference voltage is an intermediate value, -2.8 V. Hence, the node N3 is at -3.6 V if the transistor Q2 has a base-emitter voltage V.sub.BE at 0.8 V. As a result, a reference voltage V.sub.BB2 must be -3.6 V or lower so that the transistor Q3 will not reach saturation. For this requirement, the node N4 is -4.4 V if the transistor Q3 has a base-emitter voltage V.sub.BE of 0.8 V. In other words, a supply voltage V.sub.D has to be at -4.4 V or lower so that a transistor Q7 will not reach saturation. A node N5 takes a voltage of -5.2 V if the transistor Q7 has a base-emitter voltage V.sub.BE of 0.8 V. Now, if the voltage to be applied to a resistor R.sub.D is 0.4 V, the power supply V.sub.T2 must be no higher than -5.6 V. When this happens, the circuit shown in FIG. 3 cannot be used in a memory LSI which is usually used with a power supply of 5.2 V.